Integrated circuit fabrication may involve implanting one or more dopants into a semiconductor substrate. One method for implanting dopant into the substrate is beamline ion implantation. Such method can utilize high energy to implant ions deeply into a substrate. However, as semiconductor devices become increasingly smaller (i.e., as a level of integration increases) multiple problems are encountered in attempting to utilize beamline ion implantation. Such problems include fundamental physical limits pertaining to the space charge limit, sputtering limit, and the implant angle limit for non-planar structures.
Another method for implanting dopant into a semiconductor substrate is plasma doping (PLAD), which may be also referred to as plasma immersion ion implantation (PIII). PLAD may offer advantages relative to beamline ion implantation such as system simplicity, lower-cost and higher throughput; and further may not be adversely affected by the fundamental physical limits that reduce the scalability of beamline ion implantation. However, PLAD can suffer from a disadvantage in that it is difficult to implant dopant deeply into a substrate. Further, PLAD often forms an undesired deposit across a substrate surface. The deposit can be removed with a subsequent clean, but such clean can exacerbate the problem of the shallow dopant implant occurring with PLAD. Specifically, the clean may remove some of the substrate from over the implant region and thereby render the implant to be even more shallow relative to an upper substrate surface.
In light of the above-discussed difficulties associated with conventional dopant implant methodologies, it would be desirable to develop new methods for implanting dopants into semiconductor substrates during integrated circuit fabrication.